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?2005 peregrine semiconductor corp. all rights reserved. page 1 of 11 document no. 70-0165-03 www.psemi.com rx1 rx2 rx3 rx4 tx1 tx2 cmos control/driver and esd v1 v2 v3 figure 2. package type 20-lead 4x4 mm qfn the pe4268 sp6t rf ultracmos? switch addresses the specific design needs of the quad-band gsm handset antenna switch module market. broadband performance also makes it a versatile solution in other if and rf applications. the switch includes two high power paths with low insertion loss and four low power paths with high isolation. on-chip cmos decode logic facilitates three-pin low voltage cmos control. high esd tolerance of 1500 v at all ports and no blocking capacitor requirements make this the ultimate in integration and ruggedness. the pe4268 ultracmos? rf switch is manufactured in peregrine?s patented ultra thin silicon (utsi?) cmos process, offering the performance of gaas with the economy and integration of conventional cmos. product specification sp6t ultracmos? 2.6 v switch 100 ? 3000 mhz product description figure 1. functional diagram pe4268 features ? three pin cmos logic control with integral decoder/driver ? low tx insertion loss: 0.55 db at 900 mhz, 0.7 db at 1900 mhz ? tx ? rx isolation of 48 db at 900 mhz, 40 db at 1900 mhz ? low harmonics: 2f o = -84 dbc and 3f o = -70 dbc at +35 dbm input power ? 1500 v hbm esd tolerance ? rx saw over voltage protection circuit ? harmonics immune to rx vswr ? no blocking capacitors required ? 20-lead 4x4 mm qfn package
product specification pe4268 page 2 of 11 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0165-03 ultracmos? rfic solutions table 1. electrical specifications @ +25 c, v dd = 2.6 v (z s = z l = 50 ? ) parameter condition min typ max unit operational frequency 100 3000 mhz insertion loss ant - tx - 850 / 900 mhz ant - tx - 1800 / 1900 mhz ant - rx - 850 / 900 mhz ant - rx - 1800 / 1900 mhz 0.6 0.8 0.9 1.1 0.75 0.95 1.15 1.35 db db db db isolation tx - rx - 850 / 900 mhz tx - rx - 1800 / 1900 mhz tx1 - tx2 - 850 / 900 mhz tx1 - tx2 - 1800 / 1900 mhz 46 38 28 22 50 42 30 24 db db db db return loss 850 / 900 mhz 1800 / 1900 mhz 17 15 20 18 db db 2nd harmonic 1 35 dbm tx input - 850 / 900 mhz 33 dbm tx input - 1800 / 1900 mhz -84 -80 -78 -77 dbc dbc 3rd harmonic 1 35 dbm tx input - 850 / 900 mhz 33 dbm tx input - 1800 / 1900 mhz -70 -66 -68 -63 ip3 rx input 40 dbm 1db compression rx input 20 dbm switching time (10-90%) (90-10%) rf 2 3 s dbc dbc note : 1. harmonics are characterized with a source that is 50 ? at the fundamental and reflective at the harmonics. contact applications support at help@psemi.com for more information.
?2005 peregrine semiconductor corp. all rights reserved. product specification pe4268 page 3 of 11 document no. 70-0165-03 www.psemi.com table 2. pin descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. note 1: ant port rated higher per applications section, see page 4. table 3. dc electrical specifications table 5. truth table pin no. pin name description 1 1 tx1 rf i/o - tx1 2 gnd ground 3 1 tx2 rf i/o ? tx2 4 gnd ground 5 gnd ground 6 vdd supply 7 v3 switch control input, cmos logic level 8 v2 switch control input, cmos logic level 9 v1 switch control input, cmos logic level 10 gnd ground 11 1 rx4 rf i/o - rx4 12 1 rx3 rf i/o - rx3 13 gnd ground 14 1 rx2 rf i/o - rx2 15 1 rx1 rf i/o - rx1 16 gnd ground 17 gnd ground 18 gnd ground 19 1 ant rf common ? antenna input 20 gnd ground note 1: blocking capacitors needed only when connected to an external non-zero dc voltage. symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 +150 c t op operating temperature range -40 +85 c p in tx input power (50 ? ) +38 dbm rx input power (50 ? ) +23 v esd 1 esd voltage (hbm, mil_std 883 method 3015.7) 1500 v esd voltage (mm, jedec, jesd22-a114-b) 100 v esd voltage (cdm, jedec, jesd22-c101-a) 2000 v parameter min typ max units v dd supply voltage 2.4 2.6 2.8 v i dd power supply current (v dd = 2.6v) 13 20 a control voltage high 0.7 x v dd v control voltage low 0.3 x v dd v path v3 v2 v1 ant ? rx1 0 0 0 ant ? rx2 0 0 1 ant ? rx3 0 1 0 ant ? rx4 0 1 1 ant - tx1 1 0 x ant - tx2 1 1 x figure 3. pin configuration (top view) absolute maximum ratings are those values listed in the above table. exceeding these values may cause permanent device damage. functional operation should be restricted to the limits in the dc electrical specifications table. exposure to absolute maximum ratings for extended periods may affect device reliability. v dd v3 v2 v1 gnd 1 20 19 18 17 16 15 14 13 12 11 6 7 8 9 10 2 3 4 5 tx1 gnd tx2 gnd gnd rx4 rx3 gnd rx2 rx1 gnd gnd gnd ant gnd 20-lead qfn 4x4mm exposed solder pad
product specification pe4268 page 4 of 11 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0165-03 ultracmos? rfic solutions evaluation kit the sp6t evaluation kit board was designed to ease customer evaluation of the pe4268 rf switch. the pe4268 has two high power tx ports and four high isolation rx ports. the tx ports are symmetric and are designed as paths for the 850, 900, 1800, or 1900 mhz bands. the rx ports are also symmetric and can be assigned to any of these frequency bands. the ant port connects through a 50 ? transmission line to the top sma connector, j1. the rx and tx ports connect through 50 ? transmission lines to sma connectors j2 ? j7. a through 50 ? transmission line between sma connectors j9 and j10 allows estimation of the pcb losses over environmental conditions. an open transmission line connected to j11 is also provided. j8 supplies dc power to the pin marked v dd and the bottom row of pins, which is gnd. 1 m ? pull-up resistors are connected from v dd to each of the three control logic inputs: v1, v2, and v3. these pull-up resistors are provided for ease of evaluation on this board and are not required for the pe4268 to operate. adding a jumper between a control pin and the adjacent gnd pin on the bottom row of j8 will set a logic-0 on that control pin. removing the jumper will set a logic-1. to evaluate the pe4268, add or remove jumpers according to the truth table in table 5. figure 4. evaluation board layout ant rx1 rx2 rx3 rx4 tx1 tx2 open line through-line figure 5. evaluation board schematic peregrine specification 101/0205 peregrine specification 102/0267
?2005 peregrine semiconductor corp. all rights reserved. product specification pe4268 page 5 of 11 document no. 70-0165-03 www.psemi.com -90 -70 -50 -30 -10 0 1000 2000 3000 4000 frequency (mhz) insertion loss (db) tx1-tx2 tx1-rx4 tx2-rx4 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 1000 2000 3000 4000 frequency (mhz) insertion loss (db) rx1 rx2 rx3 rx4 tx1 tx2 -2.5 -2 -1.5 -1 -0.5 0 0 1000 2000 3000 4000 frequency (mhz) insertion loss (db) 2.4 v 2.6 v 2.8 v -2.5 -2 -1.5 -1 -0.5 0 0 1000 2000 3000 4000 frequency (mhz) insertion loss (db) -40c +25c +85c typical performance data @ v dd = 2.6 v, 25 c (unless otherwise noted) figure 7. insertion loss: tx over v dd figure 9. isolation: worst case paths figure 8. insertion loss: tx over temp figure 6. insertion loss: all ports
product specification pe4268 page 6 of 11 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0165-03 ultracmos? rfic solutions -75 -65 -55 -45 -35 -25 28 30 32 34 36 38 input pow er (dbm) harmonic output power (dbm) -40c 2fo +25c 2fo +85c 2fo -40c 3fo +25c 3fo +85c 3fo -65 -55 -45 -35 -25 28 30 32 34 36 38 input power (dbm) harmonic output power (dbm) 2.4 v 2fo 2.6 v 2fo 2.8 v 2fo 2.4 v 3fo 2.6 v 3fo 2.8 v 3fo -75 -65 -55 -45 -35 -25 28 30 32 34 36 38 input power (dbm) harmonic output power (dbm) 2.4 v 2fo 2.6 v 2fo 2.8 v 2fo 2.4 v 3fo 2.6 v 3fo 2.8 v 3 fo -40 -30 -20 -10 0 0 1000 2000 3000 4000 frequency (mhz) return loss (db) ant, rx1 rx1 tx1 typical performance data @ v dd = 2.6 v, 25 c (unless otherwise noted) figure 11. tx harmonics 915mhz figure 13. tx harmonics 1900mhz figure 12. tx harmonics 915mhz figure 10. return loss: worse case paths over v dd over v dd over temp
?2005 peregrine semiconductor corp. all rights reserved. product specification pe4268 page 7 of 11 document no. 70-0165-03 www.psemi.com -65 -55 -45 -35 -25 28 30 32 34 36 38 input pow er (dbm) harmonic output power (dbm) -40c 2fo +2 5c 2 f o +8 5c 2 f o -40c 3fo +2 5c 3 f o +8 5c 3 f o typical performance data @ v dd = 2.6 v, 25 c (unless otherwise noted) figure 14. tx harmonics 1900mhz over temp
product specification pe4268 page 8 of 11 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0165-03 ultracmos? rfic solutions figure 15. package drawing (mm) 1.00 1.00 2.00 2.00 0.23 0.10 c a b exposed pad 4.00 detail a 16 15 11 5 1 6 20 10 0.50 typ 2.00 typ 0.55 2 1 detail a 0.18 0.18 0.435 0.435 seating plane 0.08 c 0.10 c 0.020 0.20 ref exposed pad & terminal pads 0.80 - c - 2.00 x 2.00 2.00 2.00 4.00 4.00 - b - - a - index area 0.25 c 2. coplanarity applies to the exposed heat sink slug as well 1. dimension applies to metallized terminal and is measured as the terminals. between 0.25 and 0.30 from terminal tip. 20-lead 4x4 mm qfn
?2005 peregrine semiconductor corp. all rights reserved. product specification pe4268 page 9 of 11 document no. 70-0165-03 www.psemi.com figure 16. marking specification figure 17. tape and reel drawing 4268 yyww zzzzz yyww = date code (year, work week) zzzzz = last five digits of psc lot number
product specification pe4268 page 10 of 11 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0165-03 ultracmos? rfic solutions table 7. ordering information esd protection circuit handset products must tolerate large esd surges at the antenna interface without damage. the iec 61000-4-2 standard specifies both 8 kv contact and 16 kv air discharges that typical handsets must survive. by itself, the pe4268 offers protection to 1.5 kv but with the addition of two inexpensive passive components, the switch can meet the levels as specified in the iec spec. figure 18 is the suggested solution for compliance with the iec standards. figure 18. esd protection circuit table 6. pe4268 antenna application test results (c=150 pf, r=330 ? , iec 61000-4-2 standard) l = 27 nh (murata: lqg1127nj00), c = 33 pf (murata: grm33c0g330j50) test condition results +8 kv contact discharge, 10 times with 1s intervals pass -8 kv contact discharge, 10 times with 1s intervals pass +16 kv air discharge, 10 times with 1s intervals pass -16 kv air discharge, 10 times with 1s intervals pass order code part marking description package shipping method 4268-01 4268 pe4268-20qfn 4x4mm-75a 20-lead 4x4mm qfn 75 units / tube 4268-02 4268 pe4268-20qfn 4x4mm-3000c 20-lead 4x4mm qfn 3000 units / t&r 4268-00 PE4268-EK pe4268-20qfn 4x4mm-ek evaluation kit 1 / box 4268-51 4268 pe4268g-20qfn 4x4mm-75a green 20-lead 4x4mm qfn 75 units / tube 4268-52 4268 pe4268g-20qfn 4x4mm-3000c green 20-lead 4x4mm qfn 3000 units / t&r pe4268 esd protection
?2005 peregrine semiconductor corp. all rights reserved. product specification pe4268 page 11 of 11 document no. 70-0165-03 www.psemi.com sales offices the americas peregrine semiconductor corporation 9450 carroll park drive san diego, ca 92121 tel 858-731-9400 fax 858-731-9499 north asia pacific peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213 peregrine semiconductor, korea #b-2402, kolon tripolis, #210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-480 s. korea tel: +82-31-728-4300 fax: +82-31-728-4305 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f- 92380 garches, france tel: +33-1-47-41-91-73 fax : +33-1-47-41-91-73 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intende d changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liabilit y for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos and harp are trademarks of peregrine semiconductor corp. south asia pacific peregrine semiconductor, china shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 space and defense products americas: tel: 505-881-0438 fax: 505-881-0443 europe, asia pacific: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33(0) 4 4239 3361 fax: +33(0) 4 4239 7227

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